The present invention relates to a method of producing a semiconductor device, and more particularly to a method of producing a MOS transistor of double implanted LDD (Lighty Doped Drain) structure.
A conventional MOS transistor is produced as shown in FIG. 1 wherein the method therefor comprises the steps of forming a gate oxide film 2 on a p type silicon substrate 1, subjecting it to an ion implantation to provide a channel region 3, and thereafter ion implanting arsenic (AS) in self-alignment manner using a gate electrode 4, thereby forming an n.sup.+ type drain region 5a and an n.sup.+ type source region 5b. However, in the MOS transistor thus formed, an electric field concentrates on a portion of the n.sup.+ type drain region 5a in contact with the channel region 3 and hole-electron pairs are produced at the portion. For this reason, there appear phenomena that a substrate current increases so that electrons are injected into the gate electrode 4, resulting in the problem that the operational stability is degraded.
On the other hand, also known is a transistor of LDD (Lighty Doped Drain) structure as shown in FIG. 2 wherein an n.sup.- type drain region 6a and an n.sup.- type source region 6b are provided in the vicinity of the gate oxide film 2. The transistor provides relaxation of electric field concentration in the vicinity of the drain region 6a. However, even if such LDD transistor is employed, there is a channel region of high concentration. This leads to the drawback that the threshold voltage V.sub.th increases due to the back gate bias effect.
To overcome this drawback, as shown in FIG. 3, another type of the transistor of the double implanted LDD structure has been proposed wherein p type regions 7a and 7b are formed below the n.sup.- type drain region 6a and the n.sup.- type source region 6b. Such double implanted LDD transistor does not require high energy ion implantation for suppressing short channel effect, and therefore there is not any increase in the threshold voltage V.sub.th due to the back gate bias effect.
However, where such MOS transistor of double implanted structure is produced to form the n.sup.- type region, the p type region and the n.sup.+ type region, three ion implantations are required, resulting in the problem that the process becomes complicated.